1. Field of the Invention
The present invention provides a shift register and a gate driving circuit composed of the shift registers, and more particularly, to an LCD with double frame rate utilizing the provided shift register.
2. Description of the Prior Art
FIG. 1 is a diagram illustrating a conventional LCD with double frame rate (120 Hz). As shown in FIG. 1, the LCD 100 comprises a gate driving circuit 110, two data driving circuits 121 and 122, and a display area 130. The display area 130 comprises an upper display area 131 and a lower display area 132. The data driving circuit 121 is disposed at the upper end of the display area 130 for transmitting corresponding frame data to the upper display area 131 through data lines D1, D2, and so on. The data driving circuit 122 is disposed at the lower end of the display area 130 for transmitting corresponding frame data to the lower display area 132 through data lines D1′, D2′, and so on. Each of the upper and the lower display areas 131 and 132 comprises a plurality of gate lines (G1˜G1080), a plurality of data lines, and a plurality of pixels P. The plurality of pixels P are interwoven by the plurality of gate lines and the plurality of data lines. Each pixel P comprises a thin film transistor (TFT) SW, a pixel capacitor CST, and a corresponding liquid crystal particle CLC. The gate of the TFT SW is coupled to a corresponding gate line, the source of the TFT SW is coupled to a corresponding data line, and the drain of the TFT SW is coupled to the corresponding pixel capacitor CST and the corresponding liquid crystal particle CLC.
The gate driving circuit 110 comprises four gate drivers 111˜114. For example, the amount of the total gate lines of the LCD 100 may be 1080, and consequently the gate driver 111 corresponding to the upper display area 131 comprises gate lines G1˜G270, the gate driver 112 corresponding to the upper display area 131 comprises gate lines G271˜G540, the gate driver 113 corresponding to the lower display area 132 comprises gate lines G541˜G810, the gate driver 114 corresponding to the lower display area 132 comprises gate lines G811˜G1080. The gate driving circuit 110 is disposed for receiving down-scanning enabling signal ID and transmitting gate driving signals S1, S2 . . . S540 and S541, S542 . . . S1080 from top to bottom, or, for receiving up-scanning enabling signal IU and transmitting gate driving signals S540, S539 . . . S1 and S1080, S1079 . . . S541 from bottom to top.
FIG. 2 is a timing diagram illustrating when the gate driving circuit 110 in FIG. 1 receives the down-scanning enabling signal ID. As shown in FIG. 2, when the gate driver 111 receives the down-scanning enabling signal ID, the gate driving signals S1˜S270 are sequentially generated, and then the gate driving signal S270 is transmitted to the gate driver 112 to activate the gate driver 112 to generate the gate driving signals S271˜S540. Meanwhile, the gate driver 113 also receives the down-scanning enabling signal ID, and the gate driving signals S541˜S810 are generated, and then the gate driving signal S540 is transmitted to the gate driver 114 to activate the gate driver 114 to generate the gate driving signals S811˜S1080. In this way, the scanning processes of the upper and the lower display areas 131 and 132 are completed so as to display a frame completely.
FIG. 3 is a timing diagram illustrating when the gate driving circuit 110 in FIG. 1 receives the up-scanning enabling signal IU. As shown in FIG. 3, when the gate driver 112 receives the up-scanning enabling signal IU, the gate driving signals S540˜S271 are sequentially generated, and then the gate driving signal S271 is transmitted to the gate driver 111 to activate the gate driver 111 to generate the gate driving signals S270˜S1. Meanwhile, the gate driver 114 also receives the up-scanning enabling signal IU, and the gate driving signals S1080˜S811 are generated, and then the gate driving signal S811 is transmitted to the gate driver 113 to activate the gate driver 113 to generate the gate driving signals S810˜S540. In this way, the scanning processes of the upper and the lower display areas 131 and 132 are completed so as to display a frame completely.
Therefore, at the frame rate of 120 Hz, the upper display area 131 can generate gate driving signals with the gate drivers 111 and 112, and the lower display area 132 can generate gate driving signals with the gate drivers 113 and 114. In this way, the LCD 100 is driven completely. The amount of the gate drivers which each display area needs is 2N (N: integer). The drawback of the conventional LCD 100 is that the amount of the gate drivers cannot be reduced, which increases costs and lowers the yielding rate of the LCD.